Operating characteristics of semiconductor devices change under a variety of conditions often referred to as process, voltage, temperature (PVT) variations. The PVT variations may be variations in manufacturing process or variations in operating conditions such as junction temperature/ambient temperature and supply voltage levels. Process variations are determined at time of manufacture of the semiconductor device, while temperature and voltage variations occur while the semiconductor device is in use.
A collection of process, voltage and temperature parameters or conditions is referred to as a PVT corner or a silicon corner. Operating characteristics of a semiconductor device may vary across PVT corners. For a particular PVT corner/silicon corner if a device exhibits different operating characteristics under different supply voltage conditions, then the device is said to exhibit voltage variations. For a particular silicon corner if a device exhibits different operating characteristics under different temperature conditions, then the device is said to exhibit temperature variations.
Conventional portable electronic devices such as a radio hand set, a cellular phone or a personal digital assistant use a battery as a power source. In such electronic devices, the battery should be inserted with its polarities matching with the positive terminal (+) and negative terminal (−) of the power supply input. If the battery is inserted with the polarities (+) and (−) inverted in the portable electronic device, the inverted battery may cause internal circuits to operate improperly, shorten the life of the electronic device, or it can also damage the electronic device.
Referring to FIG. 1, a conventional automatic polarity conversion circuit 100 is disclosed. The conventional polarity conversion circuit 100 comprises a first input terminal 110, a second input terminal 120, a converter 130, a first output terminal 140 and a second output terminal 150. The first input terminal 110 and second input terminal 120 receive a first input signal and a second input signal respectively. The first input signal has a first polarity and the second input signal has a second polarity. The converter 130 converts the first input signal and second input signal into a first output signal and a second output signal respectively, wherein the first and second output signals have predetermined first output polarity and second output polarity respectively. The first output terminal 140 outputs a first signal and the second output terminal 150 outputs a second signal.
The converter 130 comprises a first transmission gate T1, a second transmission gate T2, a third transmission gate T3 and a fourth transmission gate T4. The first transmission gate T1 is constituted by a PMOS (P-channel Metal Oxide Semiconductor) transistor 10 and a NMOS (N-channel Metal Oxide Semiconductor) transistor 12 coupled to each other. The first transmission gate T1 comprises an input port, which is coupled to the first input terminal 110 and it comprises an output port, which is coupled to the first output terminal 140. The second transmission gate T2 comprises a PMOS transistor 14 and a NMOS transistor 16 coupled together. The second transmission gate T2 comprises an input port, which is coupled to the first input terminal 110 and it comprises an output port, which is coupled to the second output terminal 150. The third transmission gate comprises a PMOS transistor 18 and a NMOS transistor 20 coupled together. The third transmission gate T3 comprises an input port, which is coupled to the second input terminal 120 and it comprises an output port, which is coupled to the first output terminal 140. The fourth transmission gate comprises a PMOS transistor 22 and a NMOS transistor 24 coupled together. The fourth transmission gate T4 comprises an input port, which is coupled to the second input terminal 120 and it comprises an output port, which is coupled to the second output terminal 150.
A gate terminal of the NMOS transistor 12 is coupled to the first input terminal 110 and a gate terminal of the PMOS transistor 10 is coupled to the second input terminal 120. A gate terminal of the NMOS transistor 16 is coupled to the second input terminal 120 and a gate terminal of the PMOS transistor 14 is coupled to the first input terminal 110. A gate terminal of the NMOS transistor 20 is coupled to the second input terminal 120 and a gate terminal of the PMOS transistor 18 is coupled to the first input terminal 110. A gate terminal of the NMOS transistor 24 is coupled to the first input terminal 110 and a gate terminal of the PMOS transistor 22 is coupled to second input terminal 120.
Referring to FIG. 2, a flow chart 200 illustrates the operation of the conventional automatic polarity converter 100. In a first step 210, a first input signal having a first polarity is received by the first input terminal 110 and a second input signal having a second polarity is received by the second input terminal 120. In a second step 220, the first input signal is transferred to the first output terminal 140 through the first transmission gate T1, wherein the first input signal has a positive polarity (−). In a third step 230, the first input signal is transferred to the second output terminal 150 through the second transmission gate T2, wherein the first input signal has a negative polarity (−). In a fourth step 240, the second input signal is transferred to the first output terminal 140 through the third transmission gate T3, wherein the second input signal has a positive (+) polarity. In a fifth step 250, the second input signal is transferred to the second output terminal 150 through the fourth transmission gate 14, wherein the second input signal has a negative (−) polarity.
A disadvantage of the conventional automatic polarity conversion circuit is that the transmission gates used do not have threshold voltage adjustment features for minimizing output voltage variation over Process, Voltage and Temperature parameters.
A conventional method for polarity conversion is a flyback method, wherein opposite charge is pumped into circuit nodes and charge is trapped wherever polarity change is required. A disadvantage of the conventional flyback method is that flyback circuit parameters experience a large variation over process, voltage and temperature besides the critical timing problem for charge pumping and charge trapping.
It is therefore desirable that a polarity conversion circuit be devised, which is self-compensated for variations in Process, Voltage and Temperature (PVT).